Design and Analysis of Low Power Pulse Triggered Flip-Flop

Practically, clocking system like flip-flop (FF) consumes large portion of total chip power. In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. Pulsetriggered FF (P-FF) has been considered as a popular alternative to the conventional master –slave based FF in the applications of high speed. First, a simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulsegeneration circuit can be reduced for power saving. The maximum power saving against rival designs is up to 39.4%.Compared with the conventional transmission gatebased FF design; the average leakage power consumption is also reduced by a factor of 3.52. Index Terms – Flip-flop, low power, pulse-triggered